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ds07-12525-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89680 series mb89689/p689/w689/pv680 n outline the mb89680 series is a line of single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, four operating speed control stages, timers, pwm timer, a serial interface, a uart, an a/d converter, and an external interrupt. n features ?f 2 mc-8l family cpu core ? dual-clock control system ? maximum memory space: 64 kbytes ? minimum execution time: 0.5 m s/8 mhz ? interrupt processing time: 4.5 m s/8 mhz ? i/o ports: max. 85 channels ? 21-bit timebase counter ? 8-bit pwm timer ? 8/16-bit timer ?uart ? serial i/o with 1-byte buffer ? 8-bit a/d converter ? pulse width counter ? modem signal output ? external interrupts: 16 channels ? power-on reset function ? low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) ? cmos technology n pac k ag e 100-pin plastic qfp (fpt-100p-m06) 100-pin ceramic qfp (fpt-100c-a02) 100-pin ceramic mqfp (mqp-100c-p01)
2 mb89680 series n product lineup * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) mb89p689 mb89w689 mb89pv680 classification mass-produced product (mask rom product) one-time prom product eprom product piggyback/ evaluation product (for development) rom size 60 k 8 bits (internal mask rom) 60 k 8 bits (internal prom) 60 k 8 bits (internal eprom) 60 k 8 bits (external rom) ram size 2.0 k 8 bits instruction bit length 8 bits instruction length 1 byte to 3 bytes data bit length 1, 8, 16 bits number of instructions 136 clock generator built-in minimum execution time 0.5 m s/8 mhz to 8 m s/8 mhz, 61 m s/32.768 khz interrupt processing time 4.5 m s/8 mhz to 72 m s/8 mhz, 562.5 m s/32.768 khz ports ( ) indicate dual function ports output ports (n-ch open-drain): 21 (8) output ports (cmos): 8 (0) i/o ports (n-ch open-drain): 8 (6) i/o ports (cmos): 48 (29) total: 85 (43) 8-bit pwm timer 8 bits 1 channel 8/16-bit timer/counter 8 bits 2 channels, or 16 bits 1 channel 8-bit serial i/o with 1-byte buffer 1 channel 8-bit a/d converter 8 bits 8 channels uart full-duplex double buffer transfer data length: 6 bits to 8 bits 8 baud rates selectability, external clock available pulse width counter 5-bit noise reduction circuit pulse edge detectable and selectable (rising, falling, and both edges) software modem transmission circuit 1200-bps/2400-bps modem output external interrupt 16 channels timebase timer 21 bits watch prescaler 15 bits standby mode watch mode, subclock mode, sleep mode, and stop mode process cmos power supply voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c512-20tv mb89689 part number item
3 mb89680 series n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. 2. current consumption in the case of the mb89pv680, add the current consumed by the eprom which is connected to the top socket. when operated at low speed, the product with an otprom or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? options are fixed on the mb89pv680. package mb89689 mb89p689 mb89w689 mb89pv680 fpt-100p-m06 fpt-100c-a02 mqp-100c-p01
4 mb89680 series n pin assignment (fpt-100p-m06) (fpt-100c-a02) (top view) 1 v cc 80 2 x1a 79 3 x0a 78 4 mod0 77 5 mod1 76 6 x0 75 7 x1 74 8 v ss 73 9 rst 72 10 p00 71 11 p01 70 12 p02 69 13 p03 68 14 p04 67 15 p05 66 16 p06 65 17 p07 64 18 p10 63 19 p11 62 20 p12 61 21 p13 60 22 p14 59 23 p15 58 24 p16 57 25 p17 56 26 p20 55 27 p21 54 28 p22 53 29 p23 52 30 p24 51 p97/inl7 p96/inl6 p95/inl5 p94/inl4 p93/inl3 p92/inl2 p91/inl1 p90/inl0 p87 p86 p85 p84 p83 p82 p81 p80 p77 p76 p75/bso2 p74/bsi2 p73/bsk2 v ss p72/uo2 p71/ui2 p70/uck2 p67/bso1 p66/bsi1 p65/bsk1 p64 p63/msko 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pa7/int3 pa6/int2 pa5/int1 pa4/int0 pa3/inlb n.c. avr (av cc ) v cc p57/an07 p56/an06 p55/an05 p54/an04 p53/an03 p52/an02 p51/an01 p50/an00 (av ss ) v ss pa2/inla pa1/inl9 pa0/inl8 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p25 p26 p27 p40 p41 p42 p43 p44 p30/pwm p31/buzr p32/mski p33 p34 p35/uck1 p36/ui1 p37/uo1 p60/tmo1 p61/tmo2 p62/tclk v cc
5 mb89680 series ? pin assignment on package top (mb89pv680 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 101 n.c. 109 a2 117 n.c. 125 oe 102 a15 110 a1 118 o4 126 n.c. 103 a12 111 a0 119 o5 127 a11 104 a7 112 n.c. 120 o6 128 a9 105 a6 113 o1 121 o7 129 a8 106 a5 114 o2 122 o8 130 a13 107 a4 115 o3 123 ce 131 a14 108 a3 116 v ss 124 a10 132 v cc (top view) ( mqp-100c-p01 ) 01 n.c. a0 a1 a2 a3 a4 o7 o8 ce a10 n.c. a11 o4 o5 o6 a7 a12 a15 n.c. v cc a14 a13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a9 a8 a5 a6 v cc x1a x0a mod0 mod1 x0 x1 v ss rst p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p97/inl7 p96/inl6 p95/inl5 p94/inl4 p93/inl3 p92/inl2 p91/inl1 p90/inl0 p87 p86 p85 p84 p83 p82 p81 p80 p77 p76 p75/bso2 p74/bsi2 p73/bsk2 v ss p72/uo2 p71/ui2 p70/uck2 p67/bso1 p66/bsi1 p65/bsk1 p64 p63/msko 101 132 o2 o3 v ss n.c. oe 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pa7/int3 pa6/int2 pa5/int1 pa4/int0 pa3/inlb n.c. avr (av cc ) v cc p57/an07 p56/an06 p55/an05 p54/an04 p53/an03 p52/an02 p51/an01 p50/an00 (av ss ) v ss pa2/inla pa1/inl9 pa0/inl8 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p25 p26 p27 p40 p41 p42 p43 p44 p30/pwm p31/buzr p32/mski p33 p34 p35/uck1 p36/ui1 p37/uo1 p60/tmo1 p61/tmo2 p62/tclk v cc
6 mb89680 series n pin description (continued) *1: fpt-100p-m06, fpt-100c-a02 *2: mqp-100c-p01 pin no. pin name circuit type function qfp *1 , mqfp *2 1v cc power supply pin 2 x1a a subclock crystal oscillator pins (32.768 khz) 3x0a 4 mod0 b operating mode selection pins connect to v ss (gnd) when using. 5mod1 6 x0 a main clock crystal oscillator pins (8 mhz) 7x1 8v ss power supply (gnd) pin 9rst c reset input pin 10 to 17 p00 to p07 d general-purpose i/o ports 18 to 25 p10 to p17 d general-purpose i/o ports 26 to 33 p20 to p27 f general-purpose output ports 34 to 38 p40 to p44 i general-purpose output ports 39 p30/pwm e general-purpose i/o port also serve as an 8-bit pwm. 40 p31/buzr e general-purpose i/o port also serve as a buzzer output. 41 p32/mski e general-purpose i/o port also serve as a pulse width counter. 42, 43 p33, p34 e general-purpose i/o ports 44, 45, 46 p35/uck1, p36/ui1, p37/uo1 e general-purpose i/o ports also serve as a uart i/o 1. 47, 48, 49 p60/tmo1, p61/tmo2, p62/tclk e general-purpose i/o ports also serve as an 8/16-bit timer. 50 v cc power supply pin 51 p63/msko e general-purpose i/o port also serve as a modem output. 52 p64 e general-purpose i/o port 53, 54, 55 p65/bsk1, p66/bsi1, p67/bso1 e general-purpose i/o ports also serve as a serial i/o 1 with 1-byte buffer.
7 mb89680 series (continued) *1: fpt-100p-m06, fpt-100c-a02 *2: mqp-100c-p01 pin no. pin name circuit type function qfp *1 , mqfp *2 56, 57, 58 p70/uck2, p71/ui2, p72/uo2 h general-purpose i/o ports also serve as a uart i/o 2. 59 v ss power supply (gnd) pin 60, 61, 62 p73/bsk2, p74/bsi2, p75/bso2 h general-purpose i/o ports also serve as a serial i/o 2 with 1-byte buffer. 63, 64 p76, p77 h general-purpose i/o ports 65 to 72 p80 to p87 i general-purpose output ports 73 to 80 p90/inl0 to p97/inl7 e general-purpose i/o ports external interrupt input is hysteresis input. 81 to 83 pa0/inl8 to pa2/inla e general-purpose i/o ports external interrupt input is hysteresis input. 84 v ss (av ss ) (a/d converter) power supply (gnd) pin 85 to 92 p50/an00 to p57/an07 g general-purpose i/o ports also serve as an analog input. 93 v cc (av cc ) (a/d converter) power supply pin 94 avr a/d converter reference voltage input pin 95 n.c. internally connected pins be sure to leave them open. 96 to 100 pa3/inlb , pa4/int0 to pa 7 / i n t 3 e general-purpose i/o ports external interrupt input is hysteresis input.
8 mb89680 series n i/o circuit type (continued) type circuit remarks a ? main clock (a2) (at an oscillation feedback resistor of approximately 1 m w /5.0 v) ? subclock (a1) (at an oscillation feedback resistor of approximately 4.5 m w /5.0 v * the subclock circuit in the mb89pv680 contains no oscillation feedback resistor. b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d ? cmos output ? cmos input ? pull-up resistor optional e ? cmos output ? hysteresis input ? pull-up resistor optional x1, x1a x0, x0a standby control signal * p-ch n-ch r p-ch n-ch p-ch r p-ch n-ch p-ch r
9 mb89680 series (continued) type circuit remarks f ? cmos output g ? n-ch open-drain output ? analog input h ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional i ? n-ch open-drain output ? pull-up resistor optional p-ch n-ch p-ch n-ch analo g input n-ch p-ch r n-ch p-ch r
10 mb89680 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 hz to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
11 mb89680 series n programming to the eprom on the mb89p689/w689 the mb89p689/w689 is an otprom version of the mp89680 series. 1. features ? 60-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalent to the mbm27c1001 in eprom mode (when programmed with the eprom programmer) and supporting the 4-byte programming mode 2. memory space memory space in each mode such as 60-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p689 functions equivalent to the mbm27c1001. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 60 kbytes (1000 h to ffff h ) the prom can be programmed as follows: ? programming procedure (1) set the eprom programmer to mbm27c1001. (2) load program data into the eprom programmer at 1000 h to ffff h . load option data into addresses 0fe4 h to 0ffc h of the eprom programmer. (for information about each corresponding option, see 8. setting prom options.) (3) program to 0fe4 h to 0ffc h and 1000 h to ffff h with the eprom programmer. prom 60 kb 0ffff h 00000 h 00fe4 h 00080 h 00880 h option area single chip eprom mode (corresponding addresses on the eprom programmer) i/o ram 2 kb not available 1ffff h 00000 h prom 60 kb 01000 h 01000 h 0ffff h 00fe4 h 00ffc h 00ffc h not available not available option area address
12 mb89680 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. mb89w689 erasure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolent lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minutes. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wave- lengths shorter than 4000 ?. although erasure time will be much longer than with uv source at 2537 ?, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. program, verify data verification assembly aging +150 c, 48 hrs.
13 mb89680 series 7. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 8. setting prom options the programming procedure is the same as that for the program data. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? prom option bit map notes: note that the option setting area addresses are at intervals of four addresses to support the 4-byte programming mode. in three bytes between adjacent setup addresses, the value written to the preceding setup address is mirrored. be sure to set the same data in the programmer. each bit is set to 1 as the initialized value. part no. mb89p689pf package qfp-100 compatible socket adapter sun hayato co., ltd. rom-100qf-32dp-8la address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00fe4 h vacancy readable and writable vacancy readable and writable vacancy readable and writable single/dual- clock system 1: dual clock 2: single clock reset output 1: yes 0: no power-on reset 1: yes 0: no oscillation stabilization time 11 2 18 /f ch 10 2 16 /f ch 01 2 12 /f ch 00 2 3 /f ch 00fe8 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 00fec h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 00ff0 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 00ff4 h p67 pull-up readable and writable p66 pull-up readable and writable p65 pull-up readable and writable p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 00ff8 h p97 pull-up 1: no 0: yes p96 pull-up 1: no 0: yes p95 pull-up 1: no 0: yes p94 pull-up 1: no 0: yes p93 pull-up 1: no 0: yes p92 pull-up 1: no 0: yes p91 pull-up 1: no 0: yes p90 pull-up 1: no 0: yes 00ffc h pa 7 pull-up 1: no 0: yes pa 6 pull-up 1: no 0: yes pa 5 pull-up 1: no 0: yes pa 4 pull-up 1: no 0: yes pa 3 pull-up 1: no 0: yes pa 2 pull-up 1: no 0: yes pa 1 pull-up 1: no 0: yes pa 0 pull-up 1: no 0: yes
14 mb89680 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adapter inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 3. memory space 4. programming to the eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 1000 h to ffff h . (3) program to 1000 h to ffff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg external rom 60 kb ffff h 0000 h 0880 h 0080 h 0200 h mb89pv680 address i/o ram 2 kb 1000 h register 0100 h mbm27c512 1000 h eprom 60 kb ffff h
15 mb89680 series n block diagram timebase timer cmos i/o port 0 main clock oscillator (max 8 mhz) rst x0 x1 x0a x1a p00 to p07 p10 to p17 cmos i/o port 2 p20 to p27 ram f 2 mc-8l cpu rom v cc 2, v ss 2 mod0, mod1, n.c. av cc , avr, av ss other pins 8-bit pwm timer buzzer output modem timer uart 8-bit a/d converter cmos i/o 8/16-bit timer modem output n-ch open-drain i/o n-ch open-drain output port 8 cmos i/o external interrupt 2 p30/pwm p31/buzr p32/mski p33 p34 p35/uck1 p36/ui1 p37/uo1 p50/an00 t o p57/an07 p40 t o p44 p60/tmo1 p61/tmo2 p62/tclk p63/msko p64 p65/bsk1 p66/bsi1 p67/bso1 p70/uck2 p71/ui2 p72/uo2 p73/bsk2 p74/bsi2 p75/bso2 p76 p77 p80 t o p87 p90/inl0 t o p97/inl7 pa0/inl8 t o pa3/inlb pa4/int0 t o pa7/int3 8 12 4 reset circuit (watchdog) clock controller subclock oscillator (32.768 khz) cmos i/o port 1 internal data bus internal data bus cmos i/o n-ch open-drain output port 5 n-ch open-drain output port 4 port 6 8-bit serial i/o with 1-byte buffer port 7 port 9 and port a external interrupt 1 port 3 8 8 8 4 4 5 8 8 8
16 mb89680 series n cpu core 1. memory space the microcontrollers of the mb89680 series offer 64 kbytes of memory for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end of i/o area, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89680 series is structured as illustrated below. memory space i/o register ram 2.0 kb rom 60 kb mb89689 i/o register ram 2.0 kb rom 60 kb mb89p689 mb89w689 i/o register ram 2.0 kb external rom 60 kb mb89pv680 0000 h ffff h 0fff h 1000 h 087f h 0880 h 01ff h 0200 h 00ff h 0100 h 007f h 0080 h 0000 h ffff h 0fff h 1000 h 087f h 0880 h 01ff h 0200 h 00ff h 0100 h 007f h 0080 h 0000 h ffff h 0fff h 1000 h 087f h 0880 h 01ff h 0200 h 00ff h 0100 h 007f h 0080 h vacancy vacancy vacancy
17 mb89680 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating the instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
18 mb89680 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 0 0 0 high low 01 1 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
19 mb89680 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 this address = 0100 h + 2 (rp) memory area 32 banks
20 mb89680 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (vacancy) 06 h 07 h (r/w) sycc system clock control register 08 h (r/w) smc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc timebase timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (r/w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (r/w) bzcr buzzer register 10 h (r/w) pdr5 port 5 data register 11 h (vacancy) 12 h (r/w) pdr6 port 6 data register 13 h (r/w) ddr6 port 6 data direction register 14 h (r/w) pdr7 port 7 data register 15 h (vacancy) 16 h (r/w) pdr8 port 8 data register 17 h (vacancy) 18 h (r/w) pdr9 port 9 data register 19 h (r/w) ddr9 port 9 data direction register 1a h (r/w) pdra port a data register 1b h (r/w) ddra port a data direction register 1c h (vacancy) 1d h 1e h (r/w) cntr pwm control register 1f h (w) comr pwm compare register 20 h (vacancy) 21 h 22 h (r/w) sbmr serial mode register with 1 byte buffer
21 mb89680 series (continued) note: do not use (vacancies). address read/write register name register description 23 h (r/w) sbfr serial flag register with 1 byte buffer 24 h (w) sbufw serial buffer write register (r) sbufr serial buffer read register 25 h (r) sbdr serial data register with 1 byte buffer 26 h (r/w) t2cr timer 2 control register 27 h (r/w) t1cr timer 1 control register 28 h (r/w) t2dr timer 2 data register 29 h (r/w) t1dr timer 1 data register 2a h (r/w) modc modem output control register 2b h (r/w) moda modem output data register 2c h (vacancy) 2d h (r/w) adc1 a/d converter control 1 register 2e h (r/w) adc2 a/d converter control 2 register 2f h (r/w) adcd a/d converter data register 30 h (r/w) eie1 external interrupt 1 enable register 31 h (r/w) eif1 external interrupt 1 flag register 32 h (r/w) eie2 external interrupt 2 enable register 33 h (r/w) eif2 external interrupt 2 flag register 34 h (r/w) mdc1 modem timer control 1 register 35 h (r/w) mdc2 modem timer control 2 register 36 h (r) mldh modem timer h level data register 37 h (r) mldl modem timer l level data register 38 h (r/w) smc uart serial mode control register 39 h (r/w) src uart serial rate control register 3a h (r/w) ssd uart serial status and data register 3b h (r) sidr uart serial input data register 3c h (w) sodr uart serial output data register 3d h (r/w) ssel serial i/o port switching register 3e h to 7b h (vacancy) 7c h (w) ilr1 interrupt level 1 setting register 7d h (w) ilr2 interrupt level 2 setting register 7e h (w) ilr3 interrupt level 3 setting register 7f h (vacancy)
22 mb89680 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set to the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc v ss C 0.3 v ss + 7.0 v set v cc = av cc * avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. input voltage v i v ss C 0.3 v cc + 0.3 v except p4, p7, p8 v i v ss C 0.3 v ss + 7.0 v p4, p7, p8 output voltage v o v ss C 0.3 v cc + 0.3 v l level maximum output current i ol ? 20 ma peak value l level average output current i olav ? 10 ma average value (operating current operating rate) l level total maximum output current ? i ol ? 120 ma peak value l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C20 ma peak value h level average output current i ohav ? C10 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C60 ma peak value h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 200 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
23 mb89680 series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : this values vary with the operating frequency. see figure 1. figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent of the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc , av cc 2.2* 6.0* v normal operation assurance range* (mb89689) v cc , av cc 2.7* 6.0* v normal operation assurance range* (mb89p689/w689/pv680) v cc , av cc 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a C40 +85 c 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 1 2 3 4 5 6 operating voltage (v) operation assurance range main clock operating frequency (mhz) (at an instruction cycle of 4/f ch ) figure 1 operating voltage vs. main clock operating frequency analog accuracy assured in the av cc = 3.5 v to 6.0 v range
24 mb89680 series warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
25 mb89680 series 3. dc characteristics (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih p0, p1 0.7 v cc v cc + 0.3 v v ihs p3, p6, p9, pa, rst , mod0, mod1, x0, x0a 0.8 v cc v cc + 0.3 v v ihs2 p7 0.8 v cc v ss + 7.0 v l level input voltage v il p0, p1 v ss - 0.3 0.3 v cc v v ils p3, p6, p7, p9, pa, rst , mod0, mod1, x0, x0a v ss - 0.3 0.2 v cc v open-drain output pin applied voltage v d p4, p7, p8 v ss - 0.3 v ss + 7.0 v p5 v ss - 0.3 v cc + 0.3 v h level output voltage v oh p0 to p3, p6, p9, pa i oh = C2.0 ma 2.4 v l level output voltage v ol1 p0 to p4, p6 to p9, pa i ol = 4.0 ma 0.4 v v ol2 rst i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li p0 to p9, pa, mod0, mod1 0.45 v < v i < v cc 5 m a power supply current i cc v cc f ch = 8 mhz v cc = 5.0 v main clock opration highest gear speed 1326ma i ccs1 v cc f ch = 8 mhz v cc = 5.0 v main sleep mode highest gear speed 4 8ma i ccs2 v cc f ch = 32.768 khz v cc = 3.0 v subclock sleep mode 2550 m a i cch1 v cc t a = +25 c subclock stop mode 1 m a
26 mb89680 series (continued) (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. power supply current i cch2 v cc t a = +85 c subclock stop mode 110 m a i csb v cc f cl = 32.768 khz v cc = 3.0 v subclock operation 50 100 m a i cct v cc v cc = 3.0 v watch mode 15 m a i a av cc f ch = 8 mhz 1.53.5ma when a/d conversion is activated i ah av cc 1 5 m a when a/d conversion is stopped input capacitance c in other than av cc , av ss , v cc, and v ss f = 1 mhz 10 pf
27 mb89680 series 4. ac characteristics (1) reset timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle input to the x0. (2) specifications for power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time selected. for example, when the main clock is operating at f ch = 8 mhz and the oscillation stabilization time is 2 12 /f ch , the oscillation stabilization time is 0.5 ms. therefore, the maximum value of power supply rising time is about 0.5 ms. when increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t xcyl *ns rst h pulse width t zhzl 24 t xcyl *ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc rst t zlzh t zhzl 0.2 v 0.2 v 4.5 v 0.2 v t r v cc t off
28 mb89680 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: duty = p wh /t hcyl *2: duty1= p whl /t hcyl parameter symbol pin name condition value unit remarks min. typ. max. input clock frequency f ch x0, x1 1 8 mhz main clock f cl x0a, x1a 32.768 khzsubclock clock cycle time t hcyl x0, x1 125 1000 ns main clock t lcyl x0a, x1a 30.5 m s subclock input clock duty rate duty* 1 x0 30 70 % external clock duty1* 2 x1 30 70 % input clock rising/falling time t cr1 x0 24 ns t cf1 x0 24 ns t cr2 x0a 200 ns t cf2 x0a 200 ns x0 c 1 c 0 f ch f ch x1 when a crystal or ceramic resonator is used x0 x1 when an external clock is used open 0.8 v cc x0 0.8 v cc 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc p wh p wl t hcyl main clock timing conditions main clock configurations
29 mb89680 series (4) instruction cycle (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol value (typical) unit remarks minimum execution time (instruction cycle) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s (4/f ch ) t inst = 0.5 m s when operating at f ch = 8 mhz t inst 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz x0a x1a when a crystal or ceramic resonator is used x0a x1a when an external clock is used open c 0 c 1 f cl f cl 0.8 v cc x0a 0.8 v cc 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc p whl p wll t lcyl subclock timing conditions subclock configurations
30 mb 8 96 8 0 se r i es (5 ) s e r ia l i/ o timing ( a v cc = v c c = 5 . 0 v 10% , v s s = 0 . 0 v , t a = C 4 0 c t o +85 c) * : f o r i n fo r ma t io n o n t i n s t , s e e ( 4 ) i n str u cti on c y c l e . p a ra m e t e r symbo l p i n n a m e condition v a l u e uni t rem a rks min . m a x. s e r i a l c l o c k cy c l e t i m e t s c y c b s k / uc k in t e r n a l s h i ft c l o c k m o de 2 t i n s t * m s b s k / uck ? b s o / u o ti m e t s l o v b s k / uc k , b s o / u o C2 0 0 2 0 0 ns v a l i d b s i / u i ? b s k/ u c k - t i v s h b s i / ui, b s k / uc k 1 / 2 t i n s t * m s b s k / uck - ? v a l i d b s i/ u i ho l d t i m e t s h i x b s k / uc k , b s i / u i 1 / 2 t i n s t * m s s e r i a l c l o c k h p u l s e w i dt h t s h s l b s k / uc k e x t e r na l s h i ft c l o c k m o de 1 t i n s t * m s s e r i a l c l o c k l p u l s e w i dt h t s l s h b s k / uc k 1 t i n s t * m s b s k / uck ? b s o / u o ti m e t s l o v b s k / uc k , b s o / u o 0 2 0 0 ns v a l i d b s i / u i ? b s k/ u c k - t i v s h b s i / ui, b s k / uc k 1 / 2 t i n s t * m s b s k / uck - ? v a l i d b s i/ u i ho l d t i m e t s h i x b s k / uc k , b s i / u i 1 / 2 t i n s t * m s t scyc t slov t shix t ivsh bsk/uck 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc bso/uo bsi/ui t slsh t slov t shix t ivsh bsk/uck 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc bso/uo bsi/ui 0.2 v cc t shsl 0.8 v cc in t e r nal shif t c l o c k mode external shift clock mode
31 mb89680 series (6) peripheral input timing (av cc = v cc = 5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin value unit remarks min. max. peripheral input h level pulse width t ilih inl0 to inlb, int0 to int3 2 t inst * m s peripheral input l level pulse width t ihil inl20 to inlb, int0 to int3 2 t inst * m s 0.2 v cc 0.8 v cc t ihil inl0 to inlb int0 to int3 0.2 v cc 0.8 v cc t ilih
32 mb89680 series 5. a/d converter electrical characteristics (av cc = v cc = 3.5 v to 6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. 6. a/d converter glossary ? resolution analog changes that are identifiable by the a/d converter when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin name condition value unit remarks min. typ. max. resolution avr = av cc = 5.0 v 8bit to t a l e r r o r avr = av cc 1.5 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v 0t avss C1.0 lsb avss +0.5 lsb avss +2.0 lsb mv 1 lsb = avr/256 full-scale transition voltage v fst avr C3.0 lsb avr C1.5 lsb avr mv interchannel disparity 0.5lsb a/d mode conversion time 44t inst * sense mode conversion time 12 t inst * analog port input current i ain an00 to an07 10 m a analog input voltage an00 to an07 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr avr = av cc = 5.0 v 100 300 m a i rh avr 1 m a
33 mb89680 series 7. notes on using a/d converter ? input impedance of the analog input pins the a/d converter used for the mb89890 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after starting a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx. 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = differential linearity error = analog input actual conversion value theoretical conversion value total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error sample hold circuit analog channel selector close for 8 instruction cycles after starting a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. analog input pin comparator c @ 33 pf r @ 6 k w analog input equivalent circuit
34 mb89680 series n instructions (136 instructions) execution instructions can be divided into the following four groups: ?transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
35 mb89680 series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
36 mb89680 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
37 mb89680 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
38 mb89680 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
39 mb89680 series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep ,#d8 cmp @ep ,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
40 mb89680 series n mask options n ordering information no. part number mb89689 mb89p689 mb89w689 mb89pv680 specifying procedure spcify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p60 to p67, p90 to p97, pa 0 t o pa 7 selectable by pin selectable by pin fixed to without a pull-up resistor 2 power-on reset (por) with power-on reset without power-on reset selectable selectable fixed to with power-on reset 3 oscillation stabilization time selection (osc) the initial value of the main clock oscillation stabilization time can be set with wtm1 and wtm0 bit. selectable wtm1 wtm0 00:2 3 /f ch 01:2 12 /f ch 10:2 16 /f ch 11:2 18 /f ch selectable wtm1 wtm0 00:2 3 /f ch 01:2 12 /f ch 10:2 16 /f ch 11:2 18 /f ch fixed to oscillation stabilization time of 2 18 /f ch 4 reset pin output (rst) with reset output without reset output selectable selectable fixed to with reset output 5 clock mode selection (clk) dual-clock mode single-clock mode selectable selectable fixed to dual clock part number package remarks mb89689pf mb89p689pf 100-pin plastic qfp (fpt-100p-m06) mb89w689cf 100-pin ceramic qfp (fpt-100c-a02) MB89PV680CF 100-pin ceramic mqfp (mqp-100c-p01)
41 mb89680 series n package dimensions (.0256.0060) 0.650.15 typ 0.300.05 8.89(.350)dia 0.80(.0315) typ 22.30(.878) typ 22.00(.866) typ 1.60(.063) typ (.012.002) 0.650.15 (.0256.0060) 18.85(.742)ref (.787.010) 20.000.25 23.90(.941) typ (.006.002) 0.150.05 4.45(.175)max 0.51(.020) typ ref 12.34(.486) typ 16.31(.642) typ 16.00(.630) (.551.010) typ 17.91(.705) 14.000.25 index area 1994 fujitsu limited f100013sc-1-2 c dimensions in mm (inches) 100-pin ceramic qfp (fpt-100c-a02) (.031.008) 0.800.20 lead no. (.012.004) 0.300.10 0.65(.0256)typ 0.30(.012) 0.25(.010) 100 81 80 51 50 31 30 1 22.300.40(.878.016) 18.85(.742)ref m 0.13(.005) (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.35(.486) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.53(.021)max 0.10(.004) "b" "a" 1994 fujitsu limited f100008-3c-2 c (mounting height) dimensions in mm (inches) 100-pin plastic qfp (fpt-100p-m06)
42 mb89680 series +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.35(.486)typ (.0256.0060) 0.650.15 typ 18.85(.742) (.0256.0060) 0.650.15 (.012.003) 0.300.08 1.20 .047 (.012.003) 0.300.08 max 10.82(.426) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m100001sc-1-2 c dimensions in mm (inches) 100-pin ceramic mqfp (mqp-100c-p01)
44 mb89680 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9802 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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